1. Field of the Invention
This invention relates to a semiconductor device having a switch circuit and more particularly to a semiconductor device having a switch circuit to supply voltage to word lines or bit lines of a semiconductor memory device.
2. Description of the Related Art
Conventionally, as one of semiconductor memory devices, an electrically programmable and erasable flash memory is known. FIG. 1 shows the element cross sectional structure of one memory cell in the flash memory. As shown in FIG. 1, an N-type well region 102 is formed in a P-type semiconductor substrate 101. Further, a P-type well region 103 is formed in the N-type well region 102. In the P-type well region 103, a source region 104 and drain region 105 of the memory cell which are each formed of an n+-type region are separately formed. Further, a floating gate 106 is formed above the channel region formed between the source region 104 and the drain region 105 with an insulating film (not shown) disposed therebetween. A control gate 107 is formed above the floating gate 106 with an insulating film (not shown) disposed therebetween.
A contact region 108 formed of a P+-type region is formed in the P-type semiconductor substrate 101. A contact region 109 formed of an n+-type region is formed in the N-type well region 102. Further, a contact region 110 formed of a P+-type region is formed in the P-type well region 103.
When the memory cell is operated, gate voltage Vg, drain voltage Vd and source voltage Vs are respectively applied to the control gate 107, drain region 105 and source region 104. Further, the same voltage as the source voltage Vs is supplied to the contact region 109 of the N-type well region 102 and the contact region 110 of the P-type well region 103. In addition, a ground voltage of 0V is supplied to the contact region 108 of the P-type semiconductor substrate 101.
In the memory cell, the threshold voltage as viewed from the control gate 107 varies according to the number of electrons accumulated in the floating gate 106. The memory cell stores a “1” level or “0” level of data by use of a variation in the threshold voltage. A memory cell array can be configured by arranging a plurality of memory cells which are the same as the above memory cell.
FIG. 2 is a circuit diagram showing a memory cell array of a NOR type flash memory. As shown in FIG. 2, a plurality of memory cells MC are arranged in a matrix form. The control gates of the memory cells MC which are arranged on the same row are commonly connected to a corresponding one of a plurality of word lines WL0 to WLn. The drain regions of the memory cells MC which are arranged on the same column are commonly connected to a corresponding one of a plurality of bit lines BL0 to BLm. Generally, the memory cells are divided into a plurality of blocks and the source regions of the memory cells MC of the same block are commonly connected to a corresponding one of a plurality of source lines SLi.
FIG. 3 is a diagram showing the relation between a drain current flowing in the drain of the memory cell and gate voltage supplied to the control gate at the operation time of the memory cell. As shown in FIG. 3, a state in which the number of electrons accumulated in the floating gate is relatively large, that is, a state in which the threshold voltage Vt of the memory cell is high is defined as “0” data. On the other hand, a state in which the number of electrons accumulated in the floating gate is relatively small, that is, a state in which the threshold voltage Vt of the memory cell is low is defined as “1” data.
FIG. 4 shows the bias conditions at the data readout time, program time and erase time and shows one example of values of the gate voltage Vg, drain voltage Vd and source voltage Vs which are supplied to the memory cell at the operation time.
In the data readout operation, whether data is “0” data or “1” data is determined based on whether or not a cell current flows when the gate voltage Vg=Vread, for example a voltage of 5V is applied to the control gate while preset voltage, for example, the drain voltage Vd of 1V is being supplied to the drain region. The above determination is made by comparing the cell current of the memory cell from which data is to be read out with a reference current Iref flowing in a reference cell by use of a sense amplifier (not shown).
The data erase operation is simultaneously performed for a plurality of memory cells commonly having the source and P-type well region. At the erase time, electrons are caused to flow from the floating gate to the P-type well region based on the Fowler-Nordheim tunneling phenomenon (which is hereinafter referred to as the FN tunneling phenomenon) while the gate voltage VG is set at −7V, the source voltage Vs is set at 10V, for example, and the drain voltage Vd is set into an electrically floating state. As a result, the memory cells subjected to the erase process are all set to have “1” data.
The data program operation is performed for each memory cell, that is, for each bit. For example, the bit line of the memory cell in which “0” data is to be programmed is biased to 5V so as to inject high energy electrons generated based on the channel hot electron phenomenon into the floating gate. The bit line of the memory cell in which original “1” data is kept unchanged is set at 0V. By setting the bit line at 0V, electrons are not injected into the floating gate in the non-programmed memory cell and the threshold voltage Vt is kept unchanged.
Further, in the flash memory, the program verify and erase verify operations are performed to confirm the program and erase degrees. As shown in FIG. 3, at the program verify time, gate voltage supplied to the control gate is set equal to a program verify voltage Vpv of approximately 7V which is higher than the read voltage Vread of 5V used at the readout time and the “0” data read operation is performed. Then, the program operation and the program verify operation are alternately and repeatedly performed and the program operation is terminated when data items of the memory cells to be programmed are all set to “0”.
Further, as shown in FIG. 3, at the erase verify time, gate voltage supplied to the control gate is set equal to an erase verify voltage Vev of approximately 3.5V which is lower than the read voltage Vread=5V used at the readout time and the “1” data read operation is performed. Then, the erase operation and the erase verify operation are alternately and repeatedly performed and the erase operation is terminated when data items of the memory cells to be erased are all set to “1”. Thus, a sufficiently large cell current Icell can be acquired.
The gate voltage Vg supplied to the control gate via the word line of the flash memory is set higher than the power supply voltage at the readout time, erase time or program time. The source voltage Vs supplied to the source line is set higher than the power supply voltage at the erase time. Further, the drain voltage Vd supplied to the drain via the bit line is set higher than the power supply voltage at the program time. Conventionally, the above voltages are supplied by inputting a voltage Vpp of approximately 12V from the exterior as is disclosed in ISSCC digest of technical papers, pp. 76 to 77, 1987 or the like. FIG. 5 shows a switch circuit which controls the voltage Vpp (12V) supplied from the exterior. As shown in FIG. 5, a switch 111 transfers the voltage Vpp (12V) applied to a Vpp pad 112 into an internal portion as it is.
Further, a booster circuit which can generate high voltage used for rewriting data in a chip is disclosed in a document by J. F. Dickson, “On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique”, IEEE J. Solid-State Circuits, Vol. SC-11, No. 3, pp. 374 to 378, June 1976 or the like. Further, an example in which unification of the power supply is made by use of the above booster circuit is disclosed in A. Umezawa et al., “A 5V-Only Operation 0.6 μm Flash EEPROM with Row Decoder Scheme in Triple-Well Structure,” IEEE J. Solid-State Circuits, Vol. 27, No. 11, pp. 1540 to 1546, November 1992 and thus unification of the power supply has been studied and developed.
In recent years, the flash memory is designed to be operated on lower voltage, voltage Vddh supplied to the word line or source line is approximately 0V to 10V and voltage Vddp supplied to the bit line is approximately 0V to 5V. Therefore, the withstand voltage of the element in the chip is set to approximately 10V.
FIG. 6 shows a Vd-Id characteristic of an N-type transistor with the withstand voltage of 10V. If a high voltage of approximately 12V is applied to the transistor with the above characteristic, it is operated in a snap back region as shown in FIG. 6 and there occurs a problem that the stable operation cannot be attained.
Further, in a case where the voltage Vddh supplied to the word line or source line is generated in the internal portion by use of the booster circuit and only the voltage Vddp supplied to the bit line is generated by use of a voltage Vpp of approximately 5V input from the exterior, it takes a long time to boost the voltage supplied to the word line or source line. Therefore, for example, if it is desired to program data at high speed when the device is shipped from the factory, multiple bits cannot be programmed at the same time and there occurs a problem that it takes a long time to program data.